Performance Analysis of Different 8x8 Bit CMOS Multiplier using 65nm Technology
نویسندگان
چکیده
In this paper different low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 250MHz and 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed which are Array multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multiplier and these multiplier are realized using bridge style full adder. All these multipliers are compared in terms of delay, power dissipation and power delay product. Simulation results show that the Array multiplier and Wallace tree multiplier using bridge style adder has less power delay product and is faster as compared to other CMOS multipliers.
منابع مشابه
Low Power 8x8 Bit CMOS Multiplier Using 65nm Technology
This paper presents low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed names as Braun multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multiplier and these mu...
متن کاملReducing the Power Consumption in Flash ADC Using 65nm CMOS Technology
Today, given the extensive use of convertors in industry, reducing the power consumed by these convertors is of great importance. This study presents a new method to reduce consumption power in Flash ADC in 65nm CMOS technology. The simulation results indicate a considerable decrease in power consumption, using the proposed method. The simulations used a frequency of 1 GHZ, resulting in decreas...
متن کاملReducing the Consumption Power in Flash ADC Using 65nm CMOS Technology
This paper presents a new method to reduce consumption power in flash ADC in 65nm CMOS technology. This method indicates a considerable reduction in consumption power, by removing comparators memories. The simulations used a frequency of 1 GHZ, resulting in decreased consumption power by approximately 90% for different processing corners. In addition, in this paper the proposed method was desig...
متن کاملLow Power Layout Design of Priority Encoder Using 65nm Technology
this paper provides comparative performance analysis of power and area of 4 bit priority encoder using 65nm technology. Two priority encoder approaches are presented, one with semi custom and the other with full custom. The main objective is to compare semi custom and full custom designed layout on the basis of two parameters which is power and area. Both the semi custom circuit simulation and ...
متن کاملDesign and Simulation of a 2GHz, 64×64 bit Arithmetic Logic Unit in 130nm CMOS Technology
The purpose of this paper is to design a 64×64 bit low power, low delay and high speed Arithmetic Logic Unit (ALU). Arithmetic Logic Unit performs arithmetic operation like addition, multiplication. Adders play important role in ALU. For designing adder, the combination of carry lookahead adder and carry select adder, also add-one circuit have been used to achieve high speed and low area. In mu...
متن کامل